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The present invention relates generally to integrated circuits, and in particular to a versatile and efficient method and circuitry for transformer coupled transmission gates.
Transmission gates are integrated circuits developed for applications such as data or telecommunication systems are often required to comply with standardized interface specifications and will vary depending on the standard. A transmission gate receives a signal at its input terminal and outputs the signal at its output terminal. For transmission gates connected directly to input/output pads, a high-impedance state in the event of a power-failure condition, VDD=0V, is a necessary requirement for the transmission gate not to load any external circuitry connected to it at the input pad.
FIG. 1 is a conventional transmission gate 100. A transistor M50 and a transistor M51 constitute transmission gate 100 that passes a signal from an input terminal IN to an output terminal OUT when transmission gate is on. Transistor M50 is a PMOS transistor and Transistor M51 is an NMOS transistor.
Under normal operating conditions, e.g., VDD greater than 0, internally generated control signals GATEN and GATEP turn transmission gate 100 on or off These signals could be coming from digital gates controlling the state of the transmission gate.
Under power-failure conditions, e.g., VDD=0V, control signals GATEN and GATEP drop to 0V. This turns transmission gate off. However, when the voltage at terminal IN becomes either more positive than the threshold voltage of the PMOS transistor M50 or more negative than the threshold voltage of NMOS transistor M51, transmission gate 100 turns on, effectively connecting terminal IN to terminal OUT.
More specifically, under power-failure conditions, there are two possible scenarios when the voltage at terminal IN becomes more positive than the threshold voltage of transistor M50. First, if the intrinsic pn diode between the source and bulk of transistor M50 turns on, it will short terminal IN to vdd which is at ground potential (control GATEP=0V). Second, the channel of the PMOS transistor M50 can simply turn on due to negative gate-to-source potential with gate at zero and source at positive potential.
Accordingly, transmission gate 100 does not always provide a high-impedance mode at input terminal IN under power-failure conditions. Thus, there is a need for a transmission gate circuit that remains off during power-failure conditions even if the voltage at terminal IN becomes more positive than the threshold voltage of the PMOS transistor of the transmission gate. Similar conditions hold for negative voltage at terminal IN and the NMOS transistor M51. In that either the diode D1 or the channel of M51 will turn on shorting input terminal IN to ground or output terminal, respectively.
The present invention provides a method and circuitry for a transmission gate with high impedance during power off conditions. In accordance with the teachings of the invention, included is a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. A control circuit is configured to monitor voltages on the first terminal and on a first voltage source. The control circuit is also configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistors off during power off conditions. The control circuit ensures that the first and second transistors remain off during power off conditions even when the voltage levels at the first terminals vary widely.
In one embodiment, a first bias circuit couples between the gate of the first transistor and the first control node, and a second bias circuit couples between the gate of the second transistor and the second control node.
In another embodiment, the control circuit includes a well bias circuit that is configured to bias the first bias circuit.
In another embodiment, the well bias circuit and the first bias circuit include a plurality of PMOS transistors. The well bias circuit is configured to couple a common n-well node at the most positive voltage.
Embodiments of the present invention achieve their purposes and benefits in the context of known circuit and process technology and known techniques in the electronic and process arts. Further understanding, however, of the nature, features, and advantages of the present invention is realized by reference to the latter portions of the specification, accompanying drawings, and appended claims.